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MH89625C
OPS/DID PCM SLIC Preliminary Information
Features
* Input impedance variants: - 600 - 200 + 680 // 0.1F - 200 + 560 // 0.1F Operates with a wide range of battery voltages Constant current battery feed with constant voltage fallback for long loop drive capabilities Overvoltage and short circuit protection Off-hook detection and LED indicator drive Dial pulse detection Ring trip filter with auto ring trip Ring relay driver plus three more uncommitted relay drivers Transformerless 2W to 4W conversion A/D and D/A conversion Conforms to A-Law PCM Analog and digital loopback Conforms to CCITT k.20 overvoltage surge requirements with external primary protection circuitry
ISSUE 4
May 1995
Ordering Information MH89625C MH89625C- 5 MH89625C- 6 600 200 + 680 // 0.1F 200 + 560 // 0.1F
* * * * * * * * * * * *
40 Pin DIL Package
Description
The Mitel MH89625C SLIC (Subscriber Line Interface Circuit) provides a complete interface between an off-premise telephone line and a digital switching system. All BORSCHT functions of Battery Feed, Overvoltage Protection, Ringing Feed, Line Supervision, Codec, 2-4 Wire Hybrid and Test are provided requiring only a few external components. The input impedance conforms with Chinese standard requirements. The device is fabricated using thick film hybrid technology which incorporates various technologies for high voltage capability, optimum circuit design and very high reliability.
Applications
* * * Off premise digital PBX line cards DID (Direct Inward Dial) line cards PABX, Key Systems, Central Office Equipment
VBat
LGND
LCA
GS
VREF
CA
TIP
Tip Drive
Gain Adjust
VX
VREF
CA
DSTi DSTo DSTi CSTi DSTo CSTi F1i C2i
VR Current & Voltage Sensing Constant Current & Voltage Control 2w/4w hybrid
CODEC
F1i CS SD0 SD1 SD2 SD3
Impedance Matching
RING RF2 RF1
Ring Drive
Ring Trip Filter Relay Driver 1 Relay Driver 2 Relay Driver 3 Relay Driver 4
Line Supervision
LED
SHK
RD1
RD2
RD3
RD4
Figure 1 - Functional Block Diagram
2-269
MH89625C
Preliminary Information
TIP RING IC IC IC RF1 RF2 IC VEE SHK LED CSTi DSTi C2i DSTo F1i CA RGND RD2 RD1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
IC IC IC VBAT LGND GS VAC IC LCA VDD AGND IC IC IC IC IC VREF VRLY RD4 RD3
Figure 2 - Pin Connections
Pin Description
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 Name TIP RING IC IC IC RF1 RF2 IC VEE SHK LED CSTi Description Tip Lead. Connects to the "Tip" lead of the telephone line. Ring Lead. Connects to the "Ring" lead of the telephone line. Internal Connection: This pin is internally connected. Internal Connection: This pin is internally connected. Internal Connection: This pin is internally connected. Ring Feed 1: For OPS operation, connects to the external battery backed ringing generator, see Figure 2. Ring Feed 2: For OPS operation, connects to RING through a normally closed relay contact (K1), see Figure 2. Internal Connection. This pin is internally connected. Negative Supply Voltage: (-5V) Switch Hook Detect (Output): A logic low indicates an off-hook condition. LED Drive (Output): Drives an LED directly through an internal 2.2k resistor. A logic low indicates an off-hook condition. Control ST-BUS in (Input): A TTL compatible digital input used to control the function of the filter/codec. Three modes of operation may be affected by applying to this input logic high, logic low or an 8-bit serial word, depending on the logic states of CA and F1i. Functions controlled are: power down, filter gain adjust, loopback, chip testing, and the SD outputs which control the relay drivers, ring trip circuitry and impedance selection. Data ST-BUS in (Input): A TTL compatible digital input which accepts the 8-bit PCM word from the incoming PCM bus. Clock Input (Input): A TTL compatible digital input which accepts the 2048 kHz clock. Data ST-BUS Out (Output). A three stage TTL compatible digital output which drives the 8-bit PCM word to the outgoing PCM bus. Synchronization Input (Input): A TTL compatible active low digital input enabling (in conjunction with CA) the PCM input, PCM output and digital control input. It is internally sampled on every positive edge of the clock, C2i, and provides frame and channel synchronization.
13 14 15 16
DSTi C2i DSTo F1i
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Preliminary Information
Pin Description (Continued)
Pin # 17 Name CA Description
MH89625C
Control Address (Input): A three-level digital input which enables PCM input and output, and determines into which control register (A or B) the serial data, presented to CSTi, is stored. Relay Ground: Return path for relay supply voltage. Relay Driver 2: Connects to a user provided external relay coil. A logic high at the SD1 output of the internal MT8967 codec activates this driver. An internal clamp diode from VRLY to RD2 is provided. This relay is typically used for DID reversals. Relay Driver 1. Connects to a user provided external relay coil. A logic high at the SD0 output of the internal MT8967 codec activates this driver. An internal clamp diode from VRLY to RD1 is provided. This relay is typically used for ringing. Relay Driver 3. Connects to a user provided external relay coil. A logic high at the SD2 output of the internal MT8967 codec activates this driver. An internal clamp diode from VRLY to RD3 is provided. This relay is typically used for in-test. Relay Driver 4: Connects to a user provided external relay coil. A logic high at the SD3 output of the internal MT8967 codec activates this driver. An internal clamp diode from VRLY to RD4 is provided. This relay is typically used for out-test. Relay Positive Supply Voltage: Normally +5V. Connects to the relay coil and the relay supply voltage. Voltage Reference (Input): +2.50V for the internal codec. Internal Connection: This pin is internally connected. Internal Connection: This pin is internally connected Internal Connection: This pin is internally connected Internal Connection: This pin is internally connected Internal Connection: This pin is internally connected Analog Ground. Analog and Digital Ground. Connects to System Ground. Positive Supply Voltage (+5V) Loop Current Adjust (Input). The maximum constant loop current is a function of the resistance connected from this pin to VEE. Normally left open Internal Connection. This pin is internally connected. Battery AC Component (Input). AC noise present in the VBAT supply, isolated from the DC component, can be applied to this pin to reduce longitudinal noise on TIP and RING. To implement this feature, connect a 0.1F 100V capacitor from VBAT to VAC, and a 1k resistor from VAC to AGND. This pin must be tied to AGND when not used. Gain Setting (Input). A logic low at this input adds an additional -0.5dB gain in the receive direction (DSTi to Tip-Ring). This gain is in addition to the gain set by the Codec. A logic high adds 0dB gain. Loop Ground. Return path for the battery (VBAT) supply voltage. Connects to System Ground. Battery Supply Voltage. Normally -48V. Internal Connection: This pin is internally connected Internal Connection: This pin is internally connected Internal Connection: This pin is internally connected
18 19
RGND RD2
20
RD1
21
RD3
22
RD4
23 24 25 26 27 28 29 30 31 32 33 34
VRLY VRef IC IC IC IC IC AGND VDD LCA IC VAC
35
GS
36 37 38 39 40
LGND VBat IC IC IC
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MH89625C
Functional Description
The Mitel MH89625C OPS SLIC (Off-Premise Subscriber Line Interface Circuit) provides a complete interface between an off-premise telephone line and an digital switching system. All BORSCHT functions are provided requiring only a few external components. The input impedance conforms with Chinese standard requirements. All functions of the SLIC are controlled by the system Drive (SD) outputs of the internal Mitel A-Law Codec MT8967. The SD outputs are controlled by the serial data input stream at CSTi.
Preliminary Information
Ringing
The ringing insertion circuit has the capability to provide ringing voltage to a telephone set by simply adding an external relay, ring generator and a transient protector. The internal relay driver switches ringing voltage onto the line via the external ring relay. A clamp diode is included which suppresses voltage transients during relay switching caused by the relay coil. The serial data input at CSTi controls the internal Codec's SDo output which activates the ring driver. Refer to Table 1 for control of SLIC functions.
Supervision
The loop detection circuit determines whether a low enough resistance is across Tip and Ring to be recognized as an off-hook condition. When an off-hook condition occurs, the SHK and LED (the LED output can drive an LED directly) outputs toggle to a low level. These outputs also toggle with incoming dial pulses. During applied ringing (ring relay driver activated), the loop detection circuit engages a ringing filter. This filter prevents false off-hook detection due to the current associated with the AC ringing voltage as well as current transients that occur when the ringing voltage is switched in and out. The ring trip detection circuitry deactivates the ring relay driver after an off-hook condition is detected.
The BORSCHT Functions
The MH89625C performs all of the BORSCHT functions of Battery Feed, Overvoltage Protection, Ringing, Supervision, Codec, Hybrid and Test.
Battery Feed
The MH89625C powers the telephone set with constant DC loop current for short lines and automatically reverts to constant voltage for long lines. The constant loop current is a function of the resistance connected from the LCA pin to VEE. 147.2 -ILoop (0.0001176 X ILoop) -0.002586 Where ILoop is the desired constant loop current in mA, and R is the resistance from pin LCA to pin VEE in ohms.
R (k)
R=
Codec
The Codec function of the SLIC is implemented using the Mitel MT8967 A-Law Codec. This device provides the conversion interface between the voiceband analog signals of a telephone subscriber loop and the digital signals required in a digital PCM (pulse code modulation) system. Eight-bit PCM encoded digital data enters and leaves the chip serially on DSTi and DSTo pins, respectively. For detailed information on the CODEC portion of the MH89625C, refer to the MT8967 integrated PCM Filer/Codec data sheet (Microelectronics Digital Communications Handbook, Mitel Semiconductor Issue 9).
open
348k
200k
80k 34.0
50k 40.2
30k 49.7
ILoop (mA)
22.0
25.0
27.1
Overvoltage Protection
The MH89625C is protected from short term (20ms) transients (+250V) between TIP and RING, TIP and ground, and RING and ground. However, additional protection circuitry may be needed depending on the requirements which must be met. Normally simple external shunt protection as shown in Figure 4 is all that is required.
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Preliminary Information
Absolute Maximum Ratings* - All voltages are with respect to AGND unless otherwise specified.
Parameter 1 2 3 4 5 6 DC Supply Voltage DC Battery Voltage x DC Ring Relay Voltage DC Reference Voltage AC Ring Generator Voltage DC Digital Input Voltage
GS, CSTi
MH89625C
.
Symbol VDD VEE VBAT VRLY VREF
Min -0.3 0.3 0.3 -0.3 -0.3
Max 7 -7 -65 7 VDD 150
Units V V V V VRMS V
-0.3
VDD
DSTi, C2i F1i 7 8 DC Digital (3-level) Input voltage Storage Temperature CA TS VEE -40 VDD +125 V C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. x LGND is connected to AGND
Recommended Operating Conditions
Parameters 1 2 3 4 5 DC Supply Voltages DC Battery Voltage x DC Ring Relay Voltage DC Reference Voltage y AC Ringing Generator Voltage Ringing Generator Frequency Operating Temperature TOP Sym VDD VEE VBAT VRLY VREF 2.488 22 Min 4.75 -4.75 -39.8 Typ 5.0 -5.0 -48 5.0 2.500 90 25 Max 5.25 -5.25 -60 7 2.512 130 28 Units V V V V V VRMS Hz Test Conditions
6
0
25
70
C
x LGND is connected to AGND. y Temperature coefficient of VREF should be better than 100ppm/C. Typical figures are at 25C and are for design aid only: not guaranteed and not subject to production testing.
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MH89625C
DC Electrical Characteristics
Characteristics 1 Supply and Battery Current x IDD IEE IBAT IBAT PC 100 150 1500 2 VOL VOH VOL VOH IOL ICD -0.3 3.7 2.0 65 100 0.5 5.25 3.0 8.7 8.4 23.5 1.5 15 15 28 2 Sym Min Typ Max
Preliminary Information
Units mA mA mA mA mW mW mW A V V V V mA mA
Test Conditions LCA = Open
Short Loop Open Loop 2 Power Consumption x On-Hook (VBAT) Powerdown (VDD and VEE) Off-Hook (VDD,VEE,VBAT) REF SHK LED RD1 RD2 RD3 RD4 GS DC Reference Voltage Mean Current Low Level Output Voltage High level Output Voltage Low Level Output Voltage y High Level Output Voltage Sink Current, Relay to VDD Clamp Diode Current
RLoop = 0 RLoop = Open LCA = Open RLoop =Open RLoop = 0
3 4 5 6
IOL = 2mA IOH = 2mA IOL = 1.1mA IOH = 0.7mA VOL = 1.0V
7 8 9
Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current Low Level Input Voltage Intermediate Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current High Level Input Current Low Level Output Voltage High Level Input Voltage Tri-State Leakage Current Low Level Input Voltage High Level Input Voltage Low Level Input Current High Level Input Current
VIL VIH IIL IIH VIL VIM VIH IIL IIM IIH VOL VOH IOZ VIL VIH IIL IIH
0.8 2.0 1 1 0.0 2.4 -3.5 0.8 10 10 10 0.4 4.0 0.1 0.8 2.4 10 10
V V V V V A A V V mA V V A A VIL = 0V VIH = 5.0V VIL = 5.0V VIM = 0.5V VIH = 5.0V IOL = 1.6mA IOH = 0.1mA VIL = 0V VIH = 5.0V
CA 10 RD
11
DSTo
12 13
CSTi DSTi C2i F1i
DC Electrical Characteristics are over Recommended Operating Conditions with VDD at +5.0V 5% and VEE at -5.0V 5% unless otherwise stated. Typical figures are at 25C with nominal 5V supplies and are for design aid only. x Supply current and power consumption characteristics are over Recommended Operating Conditions with V DD at 5.0V, V EE at -5.0V and V BAT at -48.0V y The LED output consists of a 2.2k resistor in series with the SHK HCT output. NOTE 1: Powerdown mode is activated through the CSTi input data stream. Refer to Table 2.
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Preliminary Information
Loop Electrical Characteristics Characteristics 1 2 3 Maximum AC Ringing x Current Rejection Ring Trip Detect Time y Hook Switch Detect Time: Off-Hook to On-Hook On-Hook to Off-Hook Operating Loop Currents Maximum Operating Loop Current Operating Loop Resistance Loop Current at Off-Hook z Detect Threshold IIP RIP ISH 18 0 0 7 10 22 50 Sym Min 33 100 20 20 26 1850 2300 13 Typ Max Units mA ms ms ms mA mA
MH89625C
Test Conditions 25Hz, VBAT = -48V
4 5 6
LCA= Open LCA= 30k to VEE VBAT= -40V VBAT=-48V
Loop Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C with nominal 5V supplies and are for design aid only. x The SLIC can be loaded with an AC impedance as low as 4000 without generating a false SHK output. Since each REN represents 8k, the SLIC can drive a REN of 2 without generating a false SHK output. y This parameter is over Recommended Operating Conditions as well as the specified Operating Loop Resistance. z Off-Hook Detect (SHK) will be detected for loop lengths of 2900 or less.
AC Electrical Characteristics
Characteristics 1 2-wire Input Impedance x (Magnitude) (Magnitude) 2 600R 560 Network 680 Network 14 18 14 40 46 16 20 16 PSRR VDD VEE VBAT Sym Zin 600 720 813 23 24 35 54 51 52 41 52 Min Typ Max Units dB dB dB dB dB dB dB dB 300 Hz 500-2000 Hz 3400 Hz 300-600 Hz 600-3400 Hz 300 Hz 500-2500 Hz 3400 Hz Test Conditions 1020 Hz
Return Loss at 2-Wire y
3 4
Longitudinal to Metallic Balance Transhybrid Loss
5
Power Supply Rejection Ratio at 2-Wire and DSTo:
Ripple 50mV 1020 Hz 20 20 20
40 30 40
dB dB dB
AC Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C and are for design aid only. x Three impedance selections of Zin = 600, Zin=200 + 560 // 0.1F, and Zin=200 + 680 // 0.1F are available. y Values apply for all three impedances selections; in all three cases Z in = Reference Impedance. Note 1: All of the above test conditions use 200Hz to 3400 Hz unless otherwise stated. Note 2: The transmit codec gain is set to 0dB, the receive codec gain is set to 0dB, and the receive gain adjustment is set to 0dB (GS=5V), unless otherwise specified. Note 3: With the transmit and receive gains set to 0dB; 0dBmO at the DSTi input will appear as 0dBm at the Tip-Ring output; 0dBm at the Tip-Ring input will appear as 0dBmO at the DSTo output. Note 4 All dBm is referenced to 600.
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MH89625C
AC Electrical Characteristics - Transmit (A/D) Path
Characteristics 1 2 3 Absolute Gain Default (Codec 0dB) Gain Programmable Range x Loss Distortion with Frequency (relative to level at 1020Hz with codec at 0dB) Sym Min -0.5 0 0.0 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.25 -0.25 -0.5 -1.5 3.14 3.14 Typ 0 Max 0.5 7 1.0 0.75 0.35 0.55 1.5 0.25 0.25 0.5 1.5
Preliminary Information
Units dB dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm0
Test Conditions Input -6dBm 1020 Hz 1020 Hz 0-200 Hz 200-300 Hz 300-400 Hz 400-600 Hz 600-2400 Hz 2400-3000 Hz 3000-3400 Hz Input 1020 Hz 0 to + 3dBm -40 to 0dBm -50 to -40dBm -55 to-50dBm THD < 5% Input 1020 Hz THD < 5% Input 1020 Hz Input at 2-Wire 0 to -10dBm -20dBm -30dBm -40dBm -50dBm Input at 2-Wire
4
Gain Variation with Input Level (relative to gain at 1020Hz with -6dBm input)
5 6 7
Signal input Overload Level at 2-Wire Signal Output Overload Level at DSTo Signal to Total Distortion Ratio at DSTo
35 33.8 28.8 19.5 14.5
dB dB dB dB dB
8
Out-of-Band Discrimination at DSTo: Signals in 4.6 -72 kHz band Signals in 300 -3400 Hz band other than 1020Hz Signals in 4.6 -72 kHz band Harmonic Distortion (2nd or 3rd Harmonic) at DSTo Idle Channel Noise at DSTo -72
-50 -40 -25 -41 -64
dBm0 dBm0 dBm0 dB dBm0p
-25dBm, 4.6 -72kHz 0dB, 1020 Hz 0dBm, 300-3400 Hz
9 10
AC Gain Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C with nominal 5V supplies and are for design aid only. x Codec provides adjustment in 1 dB steps. Note 1: With the transmit gain set to 0dB; 0dBm at the Tip-Ring input will appear as 0dBmO at the DSTo output. Note 2: The transmit codec gain is set to 0dB unless otherwise specified. Note 3: All dBm is referenced to 600. Note 4: Refer to table 2 for control of SLIC gain. Note 5: Loss Distortion with Frequency is equivalent to the negative of Frequency Response Gain.
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Preliminary Information
AC Electrical Characteristics - Receive (D/A) Path
Characteristics 1 Absolute Gain Default 1 (Codec 0dB, GS = 5V) Default 2 (Codec 0dB, GS =oV) Gain Programmable Range GS = 5V x GS = 0V x Loss Distortion with Frequency (relative to level at 1020 Hz) with Codec at 0dB and GS =5V) Sym Min -0.5 -1.0 -7 -7.5 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.25 -0.25 -0.5 -1.5 3.14 3.14 Typ 0.0 -0.5 Max 0.5 0.0 -0 -0.5 1.0 0.75 0.35 0.55 1.5 0.25 0.25 0.5 1.5 Units dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dBm dBm0
MH89625C
Test Conditions Input -10dBm0 1020 Hz 1020 Hz Input -10dBm0 1020 Hz 1020 Hz Input -10dBm0 0-200 Hz 200-300 Hz 300-400 Hz 400-600 Hz 600-2400 Hz 2400-3000 Hz 3000-3400 Hz Input 1020 Hz 0 to +3dBm -40 to 0dBm -50 to -40dBm -55 to -50dBm THD < 5% Input 1020 Hz THD < 5% Input 1020 Hz Input at 2-Wire 0 to -20dBm -30dBm -40dBm -50dBm Input at DSTi
2
3
4
Gain Variation with Input Level (relative to gain to 1020 Hz with -10dBm0 input)
5 6 7
Signal Input Overload Level at DSTi Signal Output Overload Level at 2-Wire Signal Output to Total Distortion Ratio at 2-Wire
35 32.9 24.9 19.9
dB dB dB dB
8
Out-of-Band Discrimination at 2-wire Signals in 4.6 -72kHz band Signals in 300-3400 Hz band other than 1020 Hz Signals in 4.6 -72 kHz band
-50 -40
dBm dBm
-25dBm0, 4.6 -72 kHz 0dBm0, 1020 Hz
-25 -41
dBm dB
0dBm0, 300 -3400 Hz
9 10
Harmonic Distortion (2nd or 3rd Harmonic) at 2-Wire Idle Channel Noise at 2-Wire -73 -73
-67 -67
dBmp dBmp
Gain Setting: -3.5dB -7dB
AC Gain Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated. Typical figures are at 25C with nominal 5V supplies and are for design aid only. x Codec provides adjustment in 1 dB steps Note 1: With the transmit gain set it 0dB; 0dBm0 at the DSTi input will appear as 0dBm at the Tip-Ring output. Note 2: The receive codec gain is set to 0dB; and the receive gain adjustment is set to 0dB (GS =5V), unless otherwise specified. Note 3: All dBm is referenced to 600 Note 4: Refer to Table 2 for control of SLIC gain. Note 5: Loss Distortion with Frequency is equivalent to the negative of Frequency Response Gain.
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MH89625C
Table 1- Control of SLIC Functions through Codec 8 bit Register B Bit 7, 6 Codec Name (SLIC Name) CODEC TESTING CONTROL SD3 (RD4) SD2 (RD3) SD1 (RD2) Description
Preliminary Information
Codec Testing Controls. Set bits to 0 for normal operation. For details of testing functions, see the MT8967 integrated PCM Filter/Codec data sheet. When logic `0', SD3 goes to the open state which deactivates the internal relay driver 4, RD4 output goes to the open state. When logic `0' SD2 goes to AGND which deactivates the internal relay driver 3, RD3 output goes to the open state. A logic `0', SD1 goes to AGND which deactivates the internal relay driver 2, RD2 output goes to the open state. A logic `1', SD1 goes to VDD which activates the internal relay driver 2, RD2 output goes to RGND. A logic `0', SD0 goes to AGND which deactivates the internal relay driver 1, RD1 output goes to the open state. A logic `1', SD0 goes to VDD which activates the internal driver 1, RD1 output goes to RGND.
3 2 1
0
SD0 (RD1)
Table 2 - Modified Analog Gain* - Which when combined with CODEC gives 0dBm Variant MH89625C MH89625C-5 MH89625C-6 Input Impedance 600R 200R + 680R // 0.1F 200R + 560R // 0.1F Transmit (A/D) Path 4.02 2.72 3.26 Receive (D/A) Path -4.02 -2.72 -3.26 Units dB dB dB
* All with GS = High and A-Law CODEC (Mitel)
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Preliminary Information
Table 3- Control of SLIC Functions through GS and Codec 8 Bit Register A Bit 7 0 0 1 1 Bit 5 0 0 0 0 1 1 1 1 Bit 2 0 0 0 0 1 1 1 1
Note:
MH89625C
Special Function Control Normal Operation Digital Loopback Analog Loopback Powerdown Receive (D/A) Gain (dB)
Bit 6 0 1 0 1 Bit 4 0 0 1 1 0 0 1 1 Bit 1 0 0 1 1 0 0 1 1 Bit 3
With GS =0 0 1 0 1 0 1 0 1 Bit 0 0 1 0 1 0 1 0 1 0 -1 -2 -3 -4 -5 -6 -7
With GA = 1 -0.5 -1.5 -2.5 -3.5 -4.5 -5.5 -6.5 -7.5 Transmit (A/D) Gain (dB) 0 +1 +2 +3 +4 +5 +6 +7
A transmit gain of 0dB indicates that an analog input signal of 0dBm at Tip-Ring will appear as 0dBmO at the DSTo output. A receive gain of 0dB indicates that an input signal of 0dBmO will appear as 0dBm at the Tip-Ring output.
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MH89625C
Hybrid
The 2-4 Wire hybrid circuit separate the 2-wire balanced full duplex signal at Tip and Ring of the telephone line into 4-wire receive and transmit ground referenced analog signals internal to the SLIC. These analog signals are internally connected to the MT8967 Filter/Codec which translates the analog signals to digital PCM. The hybrid also includes cancellation circuitry which prevents the input PCM signal at DSTi from appearing at DSTo. The degree to which the Hybrid minimizes the contribution of the input signal at DSTi from appearing at the DSTo output is specified as transhybrid loss. See the Network Balance section for maximizing transhybrid loss.
Preliminary Information
Transmit Gain
Transmit Gain (Tip-Ring to DSTo) and Receive Gain (DSTi to Tip-Ring) are programmed in 1dB steps by writing to the Codec's Control Register A via the CSTi serial data stream. In addition, a Receive Gain adjustment is provided which when activated provides an additional -0.5dB gain. Refer to control of SLIC gain.
Short Circuit Protection
The MH89625C is protected from long term (infinite) short circuit conditions occurring between Tip and Ring, Tip and AGND, and Ring and AGND.
Return Loss
To maximize return loss, the impedance at Tip-Ring should match the SLIC's input impedance (Zin).
Protection Circuit Design
The high voltage protection circuit is the MH80625C which can be used in conjunction with the MH89625C to meet the CCITT K.20 specification. See Figures 3 and 4. The protection circuit consists of 1 MOSFET Transistor (BUZ 22) per 16 lines and 4 voltage clamping diodes (IN4004) per line circuit. This protection circuit will dissipate the lightning and AC power energy to protect the line circuit. The Energy Dump Ground (EDG) is tied to the chassis of the system ground. The PCB E.D.G. track to the MOSFET must be run separately. The width of the ground track should be greater than 0.050 thou and the resistance should be kept as low as possible, less than 1 ohm. The MOSFET requires a heat sink of 9C/W to dissipate the heat generated by the overvoltages
Network Balance
Transhybrid loss is maximized when the line termination impedance and the SLIC's network balance are matched. The MH89625C's network balance impedance is automatically internally set to match the SLIC's input impedance (Zin). Therefore, the SLIC's transhybrid loss is maximized when the line termination impedance and the SLIC's input impedance (Zin) are matched.
Tip-Ring Drive Circuit
The PCM input ground referenced signal at DSTi is converted to a balanced output signal at Tip and Ring. The Tip-Ring Drive Circuit is optimized for good 2-wire longitudinal balance.
Mechanical Data
See Figure 6.
Tip-Ring Receive Gain
The differential audio signal at Tip and Ring is converted to a ground referenced PCM signal at the DSTo output.
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Preliminary Information
MH89625C
MH89625C
K1A 5 K2A D1 D3 1
MH80625C
TOUT Test Out Test In
Tip
CA CSTi
17 12
8 ROUT Tip K4A K3A TIN 6 K1B K2B
R1 Q1 R2 -48V
2
F1i Ring VREF C2i
16 24 14 15 13
D2
C1
D4
to other circuit
DSTo RF2 DSTi
3 RIN Ring K4B K3B
Heat sink 9oC/W
7 8
35
GS RF1
22 K4 RELAY 20 -5V 90VRMS25Hz -48V PTC K1 RELAY 19 K2 RELAY 21 K3 RELAY 23
LED SHK
11 10 34
RD4 RD1 RD2
VAC
36
LGND
37 32 -48V
VBat RD3 LCA VRLY VDD
31
Components D1,D2,D3,D4 IN4004 Q1 = FET BUZ 22 or equivalent R1 = 10k +5% 1/4W R2 = 1k + 5% 1/4W C1 = 0.01F + 10% 100V PTC = 55, 50mA 290V TISP
VEE
9
AGND RGND
30 18
+5V
-5V
Figure 3 - Typical Line Card Application
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MH89625C
Preliminary Information
Energy Dump Ground (E.D.G)
MH80625C
IN4004 MH89625C TIP1 8 TOUT LINE 1 3 ROUT 5 6 2 RING 1 TIP LINE 16 RING 16 IN4004 IN4004 TIP 16 8 TOUT 3 ROUT
MH80625C
IN4004 5 6
MH89625C
1 TIP 2 RING
RING1
10K
S G
1K E.D.G -48V
10nF/100V Heat Sink 9oC/w
D
Figure 4 - 16 Lines Circuit Configuration
MH80625C Protection Circuit
R1 Tip
F1 Tip
To Tip and Ring of Telephone Line F2 Ring R2
To Tip and Ring of SLIC Circuitry
Ring
Notes 1) F1, 2
1/
4W 250V Slow Blow Fuse (Littlefuse 229.250 or 230.250).
2) R1, 2 5ohm 5% 1W Carbon Composition Resistor. 3) This protection circuit is available as a hybrid circuit with Mitel part number MH80625C.
Figure 5 - Solid State External Protection Application Circuit
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Preliminary Information
MH89625C
2.0 (50.8)
AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA AAAAAAAAAAAAAAAAAAAAAAA
0.180 (4.5)
0.08 (2.0)
0.020 + 0.005 (0.51 + 0.13)
0.10 + 0.01 (2.5 + 0.2)
MH89625C
1.30 +0.03 (33.0+0.8) Note 1
AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA
0.20 + 0.01 (5.0 + 0.2)
0.30 +0.02 (7.8 +0.5)
0.020 + 0.002 (0.51 + 0.051) Notes: 1) Row pitch is to the centre of the pins. 2) All dimensions are typical and in inches (mm). 3) Not to scale.
Figure 6 - Mechanical Data
2-283
MH89625C
Notes:
Preliminary Information
2-284

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